Active silicon bridge

ABSTRACT

A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.

FIELD

Integrated circuits, and more particularly, to package assemblies.

BACKGROUND

Integrated circuit (IC) product architecture often incorporates a numberof heterogeneous functions such as central processing unit (CPU) logic,graphics functions, cache memory and other system functions to createintegrated system-on-chip (SOC) designs, which may lower product designcomplexity and number of components for each product. Previously,products may have required that an end customer design a system boardusing separate packages for the different functions, which may increasea system board area, power loss, and, thus, cost of an integratedsolution.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example and not by wayof limitation in the figures of the accompanying drawings.

FIG. 1 schematically illustrates a cross-section side view of anembodiment of an integrated circuit (IC) package assembly including anembedded active bridge.

FIG. 2 schematically illustrates a cross-section of another embodimentof a portion of a package assembly including a package substrateincluding an embedded active bridge therein, the bridge containingrepeaters in signal paths through the bridge.

FIG. 3 schematically illustrates a cross-sectional side view of anotherembodiment of a package assembly including an active bridge embedded ina package substrate and including a memory controller and optionallyother protocols and a microprocessor (e.g., CPU) and memory die(s)connected to the package substrate and electrically connected to thebridge.

FIG. 4 schematically illustrates another embodiment of a packageassembly including an active bridge embedded in a package substrate anda microprocessor (e.g., CPU) and memory die(s) connected to the packagesubstrate and to the bridge.

FIG. 5 shows a high level architecture for a controller and physicalinterface for memory devices incorporated into a package assembly.

FIG. 6 illustrates an embodiment of a computing device.

DETAILED DESCRIPTION

Embodiments of the disclosure describe techniques and configurations fora package assembly including, but not limited to a package substrateincluding at least one embedded bridge.

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, wherein like numeralsdesignate like parts throughout, and in which is shown by way ofillustration embodiments in which the subject matter of the presentdisclosure may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present disclosure.Therefore, the following detailed description is not to be taken in alimiting sense, and the scope of embodiments is defined by the appendedclaims and their equivalents.

For the purposes of the disclosure, the phrase “A and/or B” means (A),(B), or (A and B). For the purposes of the disclosure, the phrase “A, B,and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, Band C).

The description may use perspective-based descriptions such astop/bottom, in/out, over/under, and the like. Such descriptions aremerely used to facilitate the discussion and are not intended torestrict the application of embodiments described herein to anyparticular orientation.

The description may use the phrases “in an embodiment,” or “inembodiments,” which may each refer to one or more of the same ordifferent embodiments. Furthermore, the terms “comprising,” “including,”“having,” and the like, as used with respect to embodiments of thepresent disclosure, are synonymous.

As used herein, the term “module” may refer to, be part of, or includean Application Specific Integrated Circuit (ASIC), an electroniccircuit, a processor (shared, dedicated, or group) and/or memory(shared, dedicated, or group) that execute one or more software orfirmware programs, a combinational logic circuit, and/or other suitablecomponents that provide the described functionality.

FIG. 1 schematically illustrates a cross-section side view of anembodiment of an integrated circuit (IC) package assembly 100 includingembedded bridge interconnect assembly 106 (hereinafter “bridge 106”). Inthis embodiment, package assembly 100 includes package substrate 104having a plurality of (e.g., two or more) dies (die 102A and die 102Bshown) mounted on a surface of package substrate 104 (a top surface asviewed). Package substrate 104, in one embodiment, includes anepoxy-based laminate substrate or body having a core and/or build-uplayers such as, for example, an Ajinomoto Build-up Film (ABF) substrate.Package substrate 104 may include other suitable types of substrates inother embodiments.

Dies 102A and 102B may be, include, or be a part of a processor, memory,or application specific integrated circuit (ASIC) in some embodiments.Each of dies 102A and 102B may represent a discrete chip. Dies 102A and102B can be attached to package substrate 104 according to a variety ofsuitable configurations including, a flip-chip configuration, asdepicted, or other configurations such as wirebonding and the like. Inthe flip-chip configuration, an active or device side of dies 102A and102B is attached to a surface of package substrate 104 (a top surface asviewed) using die interconnect structures 110 such as bumps or pillars.

In one embodiment, bridge 106 is embedded in a body of package substrate104. Bridge 106 includes active device circuitry formed therein orthereon. Active device circuitry, in one embodiment, includes at leastone active device that is a three terminal device where at least one ofthe terminals of the device can be used to control a behavior of thedevice (e.g., control electron flow). A transistor is one example of anactive device. Thus, in one embodiment, bridge 106 includes a pluralityof transistors that are configured to perform one or more functions.Examples include circuit functions such as, but not limited to,repeaters in input/output (I/O) signal paths, memory functions (e.g.,read only memory (ROM)), controllers (e.g., memory controllers), driversand test functions (e.g., lane fail-over, scan). In one embodiment,bridge 106 includes a bridge substrate or body of a semiconductormaterial such as single crystal silicon. Disposed in and/or on a surfaceof the bridge substrate or body is a device level including a pluralityof transistor devices. Such transistor devices may be connected asdesired for particular circuit functions by metallization (conductivevias and one or more metal lines or layers) connected to the devicelevel. A surface of bridge 106 (a top surface as viewed) includeselectrical routing features connected to devices or circuits of bridge106. The routing features are electrically connected to dies 102A and102B in a face-to-face (device side-to-device side) connection throughones of die interconnect structures 110. Die interconnect structures 110may be configured to route electrical signals between dies 102A and 102Band package substrate 104. In some embodiments, die interconnectstructures 110 may be configured to route electrical signals such as,for example, input/output (I/O) signals, power and/or ground signalsassociated with the operation of dies 102A and 102B.

Package substrate 104 includes electrical routing features configured toroute electrical signals to or from the dies 102A and 102B. Theelectrical routing features may be internal and/or external to thebridge 106. In one embodiment, package substrate 104 includes electricalrouting features such as external contact points (e.g., pads) configuredto receive die interconnect structures 110 and route electrical signalsto or from dies 102A. FIG. 1 shows contact points 114 and contact points116. Contact points 114 are associated with bridge 106 (e.g., vias andtraces to or from bridge 106 are connected to contact points 114). Inone embodiment, contact points 114 are configured to route input/output(I/O) signals and/or other signals between dies 102A and 102B and bridge106. In another embodiment, contact points are also used to route powerand ground signals between dies 102A and 102B and bridge 106. Contactpoints 116 are associated with the body of package substrate 104 (e.g.,vias and traces that run through the body of package substrate 104). Inone embodiment, contact points 116 are configured to route power andground and other signals between package substrate 104 and dies 102A and102B. Package substrate 104 further includes package level interconnects112 such as, for example, solder balls, connected to a surface of thepackage substrate 104 (a backside surface as viewed) to further routeelectrical signals to other electrical devices (e.g., motherboard orother chipset).

Dies 102A and 102B are electrically connected to bridge 106 through anelectrically conductive connection between ones of die interconnectstructures 110 and contact points 114 and contact points 116. In oneembodiment, bridge 106 is configured to route electrical signals betweenthe dies 102A and 102B. In one embodiment, bridge 106 is embedded in acavity of package substrate 104. In some embodiments, a portion of dies102A and 102B may overly the embedded bridge 106. In another embodiment,bridge 106 may be connected to a surface of package substrate 104similar to dies 102A and 102B.

Although two dies (dies 102A and 102B) and one bridge 106 are depictedin connection with FIG. 1, other embodiments may include more or fewerdies and bridges connected together in other possible configurationsincluding three-dimensional configurations. For example, another diethat is disposed on package substrate 104 in or out of the page relativeto dies 102A and 102B of FIG. 1 may be connected to dies 102A and 102Busing bridge 106 or another bridge.

An inset of FIG. 1 shows a magnified view of a portion of packagesubstrate 104. Package substrate 104 includes a substrate body includingsurface layer 1041 defining a superior surface of the substrate body.Surface layer 1041, in one embodiment, is a dielectric material such assolder resist or other photoimageable dielectric material. The insetshows bridge 106 embedded in the substrate body of package substrate104. Bridge 106 includes bridge substrate 1061, which may be composed ofa high resistivity/low conductivity material such as, for example, asemiconductor material such as silicon. Disposed on and/or in a surfaceof substrate 1061 is device layer 1062 including a plurality oftransistor devices and optionally other devices (e.g., capacitors).Transistor devices may be planar devices or non-planar devices (e.g.,multi-gate devices) formed according to fabrication techniques known inthe art. A backside of substrate 1061 may be connected to packagesubstrate 104 through an adhesive. Overlying device layer 1062 ismetallization layer(s) 1063. Metallization layer(s) 1063 includesconductive vias and one or more metal lines connected to ones of theplurality of devices in device layer 1062. Metallization layer 1063 mayalso include one or more routing layers (metal layers) that are notconnected to device layer 1062 but are used to directly route signalsthrough bridge 106 (passive signal lines). One or more electricalrouting features may optionally be formed on and through bridge 106 toprovide an electrical pathway between opposing surfaces (top and bottomsurfaces as viewed) of bridge 106. In an embodiment where the bridgesubstrate 1061 is composed of silicon, the one or more optional may bethrough silicon vias (TSVs) 1069.

Bridge 106 includes electrical routing features such as, for example,pads or traces and the like (referred to generally as “bridge surfacerouting features 1068”) that may be formed on a surface of bridge 106 (atop surface as viewed) to route electrical signals between dies (e.g.,dies 102A and 102B) on package substrate 104. For example, bridgesurface routing features 1068 may be electrically connected with packagerouting features formed in package substrate 104 such as, for example,vias 1042 or other routing structure. The package routing features(e.g., vias 1042), in one embodiment, are configured to be electricallyconnected with the dies (e.g., dies 102A and 102B). Where TSVs 1069 arepresent in bridge 106, bridge surface routing features 1068 may also bepresent on a bottom surface of bridge 106 to electrically connect thebridge to electrically connect the bridge to package substrate 104.

Referring to the inset of FIG. 1, package substrate 104 includes contactpoints 114.

In one embodiment, contact points 114 are conductive vias or pillars ofan electrically conductive material (e.g., copper) having a baseconnected to ones of vias 1042 and a top or superior surface availablefor an electrically conductive connection with die interconnectstructures 110 of dies 102A and 102B. In one embodiment, contact points114 are a copper material formed by electroplating a conductive materialin openings formed through surface layer 1041 (e.g., openings formed bylaser drilling or lithographic means. In one embodiment, contact points114 of package substrate 104 have a pitch, P₁, that is on the order of50 microns (μm) or less (e.g., 30 μm). Generally speaking, in oneaspect, a density of contact points 114 dictates a communication ratefor I/O type connections. Thus, a smaller or tighter pitch, P₁ (e.g., 50μm or less) corresponds to an increased communication rate relative to apitch of greater than 50 μm.

The inset of FIG. 1 also shows contact points 116 that, in oneembodiment, have a larger diameter than contact points and a pitch, P₂,that is greater than a pitch, P₁, associated with contact points 114. Inone embodiment, contact points 116 are conductive vias or pillars of anelectrically conductive material (e.g., copper or nickel) having a topor superior surface available for an electrically conductive connectionwith die interconnect structures 110 of dies 102A and 102B. Contactpoints 116 are formed, in this example, on pads or traces 109 (e.g., aredistribution layer) on a surface of the substrate body under surfacelayer 1041. Pads or traces 109 are connected to electrically conductivevias 107 that may extend directly through package substrate 104 or toconductive traces in package substrate 104 to, for example, allow forsignal transmission between dies 102A and 102B.

In one embodiment, bridge 106 may be formed according to a wafermanufacturing process. A bridge wafer is manufactured using, forexample, conventional front end of line (FEOL) and back end of line(BEOL) processes to form active devices (chips). The bridge wafer maythen be thinned and, after thinning, the wafer is singulated intoindividual bridge die which are ready for embedding in package substrate104.

In one embodiment, package substrate 104 follows a conventional build-upprocess until the final build-up layer. At this point in the process, acavity or cavities is or are introduced for a bridge (bridge 106 orbridges). A bridge is placed in a cavity, representatively held in placewith an adhesive and final layers of build-up dielectrics are appliedfollowed by fine via formation in the bridge region and coarse viaformation elsewhere. The package is now ready for chip attach (e.g., die102A and die 102B) which may be done using thermal compression bonding(TCB) followed by capillary underfill.

FIG. 2 shows a cross-sectional schematic side view of a package assemblyincluding a bridge containing active device circuitry. In thisembodiment, the active device circuitry includes repeaters. FIG. 2 showspackage assembly including package substrate 204 including bridge 206embedded therein. A configuration of package substrate 204 includingbridge 206 may be as described above with reference to FIG. 1. Connectedto a surface of package substrate 204 (a top surface as viewed) are die202A and die 202B. Each of die 202A and die 202B may be, include, or bepart of a processor, memory or ASIC. In one embodiment, each of die 202Aand die 202B is a microprocessor. In one embodiment, bridge 206 servesas a communication link between dies 202A and 202B such as communicationof I/O signals. In this embodiment, bridge 206 includes an active devicecircuitry therein in the form of repeaters. FIG. 2 schematically showsrepeater 212 and repeater 213 in bridge 206. Such repeaters are, forexample, inverters such as illustrated in the inset of FIG. 2. Repeatersreceive a signal and retransmit the signal and may be used in thisinstance to reduce a delay of a transmission signal (e.g., an RC delay).In this embodiment, die 202A and die 202B also include one or morerepeaters. Thus, for one signal path S1, FIG. 2 shows repeater 222Atherein in die 202A. The signal path S1, travels to bridge 206 whererepeater 212 is disposed in the signal path. The signal path S1, thencontinues to die 202B. FIG. 2 shows repeater 222B in signal path S1, indie 202B. Similarly, FIG. 2 shows signal path S2, in die 202A includingrepeater 223A in the signal path. Signal path S2, extends into bridge206 which shows repeater 213 in the signal path. From repeater 213,signal path S2, proceeds to die 202B and repeater 223B. Such repeatersmay be placed every half millimeter or so in signal path S1 and signalpath S2. The longer distance a signal path is, a repeater will increasedata rate and maintain signal integrity for longer distances and reducea power requirement to drive the length. The use of repeaters will alsoreduce power supply noise. In one embodiment, signal path S1 and signalpath S2 may be link matched and the repeaters can have electrostaticdischarge (ESD) protection for active devices connected to theinterfaces (e.g., interconnect structures 210) on both a bridge side(bridge 206) and a die side (die 202A and die 202B). In FIG. 2, a simplerepeater configuration is illustrated. For multiple input and outputsignals, latch repeaters may be used that, for example, provide a clocksignal (e.g., one forwarded clock) per a number of data bits sent.Finally, repeaters in a form of inverters may be configured as ringoscillators that will allow for testing of such active circuitry of thebridge without a tester as a frequency could be measured at a test padon bridge 206.

FIG. 2 also shows interconnect structures 210 connecting to power andground, in one embodiment, delivering power (P) and ground (G) to thecircuits of bridge 206 from die 202A and die 202B. If die 202A and die202B have different power supplies, in one embodiment, half the bridgecan use a power supply of die 202A and the other half can use a powersupply of die 202B with, for example, a level shifting inverter to crosspower domains on bridge 206. If die 202A and die 202B share the samepower supply, power can be shared (shorted) on bridge 206 as well.

FIG. 3 shows another embodiment of a package assembly. Package assembly300, in this embodiment, includes package substrate 304 including bridge306 embedded therein. Bridge 306 includes active device circuitry (e.g.,an active silicon bridge). Connected to a surface of package substrate304 is die 302A and die(s) 302B. Die 302A, in one embodiment, is amicroprocessor (e.g., a central processing unit (CPU)) and die(s) 302Bis a memory die (e.g., dynamic random access memory (DRAM) dies (e.g.,four to eight stacked DRAM dies). Generally, a controller and otherprotocols for a incorporating memory dies or chips into a system islocated in a microprocessor. As memory standards change (e.g., HighBandwidth Memory 2 (HBM2), HBM3, wide I/O, etc.), the microprocessormust generally change or a logic chip associated with die(s) 302B. Inthe embodiment shown in FIG. 3, the controller and other protocols forincorporating memory dies or chips into the system (e.g., reading orwriting to DRAM) is incorporated in bridge 306 rather than themicroprocessor or a logic chip associated with die(s) 302B. An activebridge in a package assembly provides a relatively low cost interfacefor a memory chip controller (MCC) or memory control unit (MCU). Asstandards change, bridge 306 can be changed rather than themicroprocessor. Still further, memory dies such as DRAM memory dies foruse in an assembly such as a package assembly 300 may be acquired from asupplier without the supplier logic die or chip.

FIG. 4 shows another embodiment of a package assembly. Package assembly400, in this embodiment, includes package substrate 404 including bridge406 embedded therein. Bridge 406 includes active device circuitry (e.g.,an active silicon bridge). Connected to a surface of package substrate404 is die 402A and die(s) 402B. Die 402A, in one embodiment, is acentral processing unit (CPU) microprocessor die and die(s) 402B is amemory die (e.g., dynamic random access memory (DRAM) dies). In thisembodiment, the active circuitry of bridge 406 includes the memorycontroller and the interface protocol that generally defines theconnectivity between the memory controller and a physical interface(PHY) for memory devices. Representatively, FIG. 5 shows a high levelarchitecture for a double date rate (DDR) memory controller andinterface (DDR PHY) incorporated in the package assembly of FIG. 4. FIG.5 shows die 402A such as a CPU in electrical communication with memorycontroller 4062 in bridge 406. Representatively, CPU includes routercircuitry 4022, memory traffic generation circuitry 4024 and clock/resetcircuitry. Bridge 406 includes memory controller 4062 electricallyconnected to DDR-PHY 4064. Bridge 406 may also include test access port4066 (e.g., Joint Test Action Group (JTAG) test access port (TAP))connected to DDR-PHY 4064. FIG. 5 further shows die(s) 402B, such asDRAM memory dies electrically connected to bridge 406.

FIG. 6 illustrates computing device 500 in accordance with oneimplementation. Computing device 500 houses board 502. Board 502 mayinclude a number of components, including but not limited to processor504 and at least one communication chip 506. Processor 504 is physicallyand electrically coupled to board 502. In some implementations at leastone communication chip 406 is also physically and electrically coupledto board 502. In further implementations, communication chip 506 is partof processor 504.

Depending on its applications, computing device 500 may include othercomponents that may or may not be physically and electrically coupled toboard 502. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

Communication chip 506 enables wireless communications for the transferof data to and from computing device 500. The term “wireless” and itsderivatives may be used to describe circuits, devices, systems, methods,techniques, communications channels, etc., that may communicate datathrough the use of modulated electromagnetic radiation through anon-solid medium. The term does not imply that the associated devices donot contain any wires, although in some embodiments they might not.Communication chip 506 may implement any of a number of wirelessstandards or protocols, including but not limited to Wi-Fi (IEEE 802.11family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution(LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,Bluetooth, derivatives thereof, as well as any other wireless protocolsthat are designated as 3G, 4G, 5G, and beyond. Computing device 500 mayinclude a plurality of communication chips 506. For instance, firstcommunication chip 506 may be dedicated to shorter range wirelesscommunications such as Wi-Fi and Bluetooth and second communication chip506 may be dedicated to longer range wireless communications such asGPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 504 of computing device 500 includes an integrated circuit diepackaged within processor 504. In some implementations, the integratedcircuit die of the processor includes one or more devices, such astransistors or metal interconnects. A package may include a packagesubstrate such as described above with one or more embedded bridges. Theterm “processor” may refer to any device or portion of a device thatprocesses electronic data from registers and/or memory to transform thatelectronic data into other electronic data that may be stored inregisters and/or memory.

Communication chip 506 also includes an integrated circuit die packagedwithin communication chip 506. In accordance with anotherimplementation, the integrated circuit die of the communication chipincludes one or more devices, such as transistors or metalinterconnects, that are formed in accordance with implementations.

In further implementations, another component housed within computingdevice 500 may contain an integrated circuit die that includes one ormore devices, such as transistors or metal interconnects.

In various implementations, computing device 500 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, computingdevice 500 may be any other electronic device that processes data.

Examples

Example 1 is a package substrate including a substrate body including aplurality of first contact points on a surface thereof configured forelectrical connection to a first die and a plurality of second contactpoints on the surface configured for electrical connection to a seconddie; and a bridge coupled to the substrate body, the bridge includingactive device circuitry that is coupled to ones of the plurality offirst contact points and ones of the plurality of second contact points.

In Example 2, the bridge of the package substrate of Example 1 isembedded in the substrate body.

In Example 3, the active circuitry of the package substrate of Example 2includes at least one repeater.

In Example 4, the at least one repeater of the package substrate ofExample 3 is disposed in a signal path between one of the plurality offirst contact points and one of the plurality of second contact points.

In Example 5, the active circuitry of the package substrate of Example 1or 2 includes control logic.

In Example 6, the active circuitry of the package substrate of Example 1or 2 includes a memory interface.

In Example 7, the first plurality of contact points of the packagesubstrate of Example 1 or 2 are operable for connection to amicroprocessor and the second plurality of contact points are operablefor connection to at least one memory die and the active circuitryincludes a memory controller.

In Example 8, the bridge of the package substrate of Example 1 or 2includes at least one passive signal line coupled to one of theplurality of first contact points and one of the plurality of secondcontact points.

In Example 9, a package assembly includes the package substrate ofExample 1 or 2; and a first die connected to the plurality of firstcontact points and a second die connected to the plurality of secondcontact points.

Example 10 is a package assembly including a package substrate bodyincluding a plurality of first contact points on a surface thereofconfigured for electrical connection to a first die and a plurality ofsecond contact points on the surface configured for electricalconnection to a second die; a bridge coupled to the substrate body, thebridge including active device circuitry that is connected to ones ofthe plurality of first contact points and ones of the plurality ofsecond contact points; and a first die coupled to the plurality of firstcontact points and a second die connected to the plurality of secondcontact points.

In Example 11, the bridge of the package assembly of Example 10 isembedded in the substrate body.

In Example 12, the active device circuitry of the package assembly ofExample 11 is configured to route input/output electrical signals.

In Example 13, the active circuitry of the package assembly of Example10 or 11 includes at least one repeater.

In Example 14, the at least one repeater of the package assembly ofExample 13 is disposed in a signal path between one of the plurality offirst contact points and one of the plurality of second contact points.

In Example 15, the active circuitry of the package assembly of Example10 or 11 includes control logic or a memory circuit.

In Example 16, the active circuitry of the package assembly of Example11 includes a memory circuit.

In Example 17, the first die of the package assembly of Example 10 is amicroprocessor and the second die is a microprocessor.

In Example 18, the first die of the package assembly of Example 11 is amicroprocessor and the second die is at least one memory die and theactive circuitry includes a memory controller.

In Example 19, the bridge of the package assembly of Example 11 includesat least one passive signal line coupled to one of the plurality offirst contact points and one of the plurality of second contact points.

Example 20 is a method of forming a package assembly includingconnecting a first die to a package substrate, the package substrateincluding a bridge substrate including active device circuitry; andconnecting a second die to the package substrate, wherein connecting thefirst die and the second die to the package substrate includesconnecting the first die and the second die to the active circuitry.

In Example 21, the active device circuitry in the method of Example 20includes a repeater.

In Example 22, the first die in the method of Example 20 is amicroprocessor and the second die is at least one memory die and theactive circuitry includes a memory controller.

In Example 23, the first die in the method of Example 19 is amicroprocessor and the second die is a microprocessor.

The above description of illustrated implementations, including what isdescribed in the Abstract, is not intended to be exhaustive or to limitthe invention to the precise forms disclosed. While specificimplementations of, and examples for, the invention are described hereinfor illustrative purposes, various equivalent modifications are possiblewithin the scope, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the abovedetailed description. The terms used in the following claims should notbe construed to limit the invention to the specific implementationsdisclosed in the specification and the claims. Rather, the scope is tobe determined entirely by the following claims, which are to beconstrued in accordance with established doctrines of claiminterpretation.

1. A package substrate comprising: a substrate body comprising aplurality of first contact points on a surface thereof configured forelectrical connection to a first die and a plurality of second contactpoints on the surface configured for electrical connection to a seconddie; and a bridge coupled to the substrate body, the bridge comprisingactive device circuitry that is coupled to ones of the plurality offirst contact points and ones of the plurality of second contact points.2. The package substrate of claim 1, wherein the bridge is embedded inthe substrate body.
 3. The package substrate of claim 2, wherein theactive circuitry comprises at least one repeater.
 4. The packagesubstrate of claim 3, wherein the at least one repeater is disposed in asignal path between one of the plurality of first contact points and oneof the plurality of second contact points.
 5. The package substrate ofclaim 2, wherein the active circuitry comprises control logic.
 6. Thepackage substrate of claim 2, wherein the active circuitry comprises amemory interface.
 7. The package substrate of claim 2, wherein the firstplurality of contact points are operable for connection to amicroprocessor and the second plurality of contact points are operablefor connection to at least one memory die and the active circuitrycomprises a memory controller.
 8. The package substrate of claim 2,wherein the bridge comprises at least one passive signal line coupled toone of the plurality of first contact points and one of the plurality ofsecond contact points.
 9. A package assembly comprising: a packagesubstrate body comprising a plurality of first contact points on asurface thereof configured for electrical connection to a first die anda plurality of second contact points on the surface configured forelectrical connection to a second die; a bridge coupled to the substratebody, the bridge comprising active device circuitry that is coupled toones of the plurality of first contact points and ones of the pluralityof second contact points; and a first die coupled to the plurality offirst contact points and a second die coupled to the plurality of secondcontact points.
 10. The package assembly of claim 9, wherein the bridgeis embedded in the substrate body.
 11. The package assembly of claim 10,wherein the active device circuitry is configured to route input/outputelectrical signals.
 12. The package assembly of claim 10, wherein theactive circuitry comprises at least one repeater.
 13. The packageassembly of claim 12, wherein the at least one repeater is disposed in asignal path between one of the plurality of first contact points and oneof the plurality of second contact points.
 14. The package assembly ofclaim 10, wherein the active circuitry comprises control logic.
 15. Thepackage assembly of claim 10, wherein the active circuitry comprises amemory circuit.
 16. The package assembly of claim 10, wherein the firstdie is a microprocessor and the second die is at least one memory dieand the active circuitry comprises a memory controller.
 17. The packageassembly of claim 10, wherein the first die is a microprocessor and thesecond die is a microprocessor.
 18. The package assembly of claim 10,wherein the bridge comprises at least one passive signal line coupled toone of the plurality of first contact points and one of the plurality ofsecond contact points.
 19. A method of forming a package assemblycomprising: coupling a first die to a package substrate, the packagesubstrate comprising a bridge substrate comprising active devicecircuitry; and coupling a second die to the package substrate, whereincoupling the first die and the second die to the package substratecomprises coupling the first die and the second die to the activecircuitry.
 20. The method of claim 19, wherein the active devicecircuitry comprises a repeater.
 21. The method of claim 19, wherein thefirst die is a microprocessor and the second die is at least one memorydie and the active circuitry comprises a memory controller.
 22. Themethod of claim 19, wherein the first die is a microprocessor and thesecond die is a microprocessor.
 23. The package substrate of claim 1,wherein the bridge comprises at least one of a transistor or a memoryelement.
 24. The package substrate of claim 1, wherein the bridgecomprises one or more through silicon vias (TSVs).
 25. The packagesubstrate of claim 1, wherein the bridge comprises a DRAM controller.26. The package substrate of claim 1, wherein the bridge comprises asemiconductor material.
 27. The package assembly of claim 9, wherein thebridge comprises at least one of a transistor or a memory element. 28.The package assembly of claim 9, wherein the bridge comprises one ormore through silicon vias (TSVs).
 29. The package assembly of claim 9,wherein the bridge comprises a DRAM controller.
 30. The package assemblyof claim 9, wherein the bridge comprises a semiconductor material. 31.The method of claim 19, further comprising: forming at least one of atransistor or a memory element in the bridge substrate.
 32. The methodof claim 19, further comprising: forming one or more through siliconvias (TSVs) in the bridge substrate.
 33. The method of claim 19, furthercomprising: forming a DRAM controller in the bridge substrate.
 34. Themethod of claim 19, wherein the bridge substrate comprises asemiconductor material.